//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under 
**  license and may only be used or copied in accordance with the terms of the 
**  license. The information in this file is furnished for informational use 
**  only, is subject to change without notice, and should not be construed as 
**  a commitment by Intel Corporation. Intel Corporation assumes no 
**  responsibility or liability for any errors or inaccuracies that may appear 
**  in this document or any software that may be provided in association with 
**  this document. 
**  Except as permitted by such license, no part of this document may be 
**  reproduced, stored in a retrieval system, or transmitted in any form or by 
**  any means without the express written consent of Intel Corporation. 
**
**  FILENAME:       xllp_icp.h
**
**  PURPOSE:        Definitions for Bulverde ICP
**
**
******************************************************************************/

#ifndef xllp_icp_h
#define xllp_icp_h

/*
************************************************************************************
*                             CONSTANTS 
************************************************************************************
*/

/*
************************************************************************************
*                            DATA TYPES 
************************************************************************************
*/

// ICP registers
typedef struct
{
    XLLP_VUINT32_T ICCR0;      // FICP Control Register 0
    XLLP_VUINT32_T ICCR1;      // FICP Control Register 1
    XLLP_VUINT32_T ICCR2;      // FICP Control Register 2
    XLLP_VUINT32_T ICDR;       // FICP Data Register
    XLLP_VUINT32_T RESERVED0;  // Reserved
    XLLP_VUINT32_T ICSR0;      // FICP Status Register 0
    XLLP_VUINT32_T ICSR1;      // FICP Status Register 1
    XLLP_VUINT32_T ICFOR;      // ICP FIFO Occupancy Status Register
    XLLP_VUINT32_T RESERVED1;  // Reserved
} XLLP_ICP_T, *P_XLLP_ICP_T;

typedef struct
{

    P_XLLP_ICP_T    pICPRegs;       // Pointer to the ICP registers
    P_XLLP_GPIO_T   pGPIORegs;      // Pointer to the GPIO registers
    P_XLLP_BCR_T    pBCRRegs;       // Pointer to the GPIO registers
    P_XLLP_CLKMGR_T pCLKMGRRegs;    // Pointer to the Clock Manager registers

    // user specified values to write to the ICP registers.
    XLLP_VUINT32_T  ICCR0_Value;      // Value to write to FICP Control Register 0
    XLLP_VUINT32_T  ICCR1_Value;      // Value to write to FICP Control Register 1
    XLLP_VUINT32_T  ICCR2_Value;      // Value to write to FICP Control Register 2

    XLLP_VUINT32_T  BCR_MISCWR1_Value; // Value to write to BCR Miscellaneous Write Register 1

} XLLP_ICP_HANDLE_T, *P_XLLP_ICP_HANDLE_T;

// Masks for FICP Control Register 0 (ICCR0)
#define XLLP_ICCR0_ITR XLLP_BIT_0
#define XLLP_ICCR0_LBM XLLP_BIT_1
#define XLLP_ICCR0_TUS XLLP_BIT_2
#define XLLP_ICCR0_TXE XLLP_BIT_3
#define XLLP_ICCR0_RXE XLLP_BIT_4
#define XLLP_ICCR0_RIE XLLP_BIT_5
#define XLLP_ICCR0_TIE XLLP_BIT_6
#define XLLP_ICCR0_AME XLLP_BIT_7

// Mask for FICP Control Register 1 (ICCR1)
#define XLLP_ICCR1  (XLLP_BIT_0 + XLLP_BIT_1 + XLLP_BIT_2 + XLLP_BIT_3 + \
                     XLLP_BIT_4 + XLLP_BIT_5 + XLLP_BIT_6 + XLLP_BIT_7)

// Masks for FICP Control Register 2 (ICCR2)
#define XLLP_ICCR2_TRIG8    0
#define XLLP_ICCR2_TRIG16   XLLP_BIT_0
#define XLLP_ICCR2_TRIG32   XLLP_BIT_1
#define XLLP_ICCR2_TXP      XLLP_BIT_2
#define XLLP_ICCR2_RXP      XLLP_BIT_3
#define XLLP_ICCR2_TRAIL    XLLP_BIT_4
#define XLLP_ICCR2_BUS      XLLP_BIT_5

// Masks for FICP Status Register 0 (ICSR0)
#define XLLP_ICSR0_EIF      XLLP_BIT_0
#define XLLP_ICSR0_TUR      XLLP_BIT_1
#define XLLP_ICSR0_RAB      XLLP_BIT_2
#define XLLP_ICSR0_TFS      XLLP_BIT_3
#define XLLP_ICSR0_RFS      XLLP_BIT_4
#define XLLP_ICSR0_FRE      XLLP_BIT_5
#define XLLP_ICSR0_EOC      XLLP_BIT_6

// Masks for FICP Status Register 1 (ICSR1)
#define XLLP_ICSR1_RSY      XLLP_BIT_0
#define XLLP_ICSR1_TBY      XLLP_BIT_1
#define XLLP_ICSR1_RNE      XLLP_BIT_2
#define XLLP_ICSR1_TNF      XLLP_BIT_3
#define XLLP_ICSR1_EOF      XLLP_BIT_4
#define XLLP_ICSR1_CRE      XLLP_BIT_5
#define XLLP_ICSR1_ROR      XLLP_BIT_6

// Mask for FICP Data Register (ICDR)
#define XLLP_ICDR   (XLLP_BIT_0 + XLLP_BIT_1 + XLLP_BIT_2 + XLLP_BIT_3 + \
                     XLLP_BIT_4 + XLLP_BIT_5 + XLLP_BIT_6 + XLLP_BIT_7)

// Mask for FICP FIFO Occupancy Register (ICFOR)
#define XLLP_ICFOR  (XLLP_BIT_0 + XLLP_BIT_1 + XLLP_BIT_2 + XLLP_BIT_3 + \
                     XLLP_BIT_4 + XLLP_BIT_5 + XLLP_BIT_6)

void XllpIcpInit(P_XLLP_ICP_HANDLE_T pICPHandle);
//void XllpIcpEnableReceive(P_XLLP_ICP_T pICPRegisters);
//void XllpIcpEnableTransmit(P_XLLP_ICP_T pICPRegisters);

#endif /* xllp_icp_h */
